1. Field of the Invention
The present invention relates to a detection and adjustment device and method, especially to a delay difference detection and adjustment device and method.
2. Description of Related Art
In a synchronous circuit, a common reference clock is necessary for different components to operate synchronously. The common reference clock is usually generated by a frequency synthesizer in accordance with a source clock. However, because the paths from the frequency synthesizer to the different components are not the same, deviations (a.k.a. time difference or phase difference) may exist among the reference clocks received by the components. This problem is called clock skew, and a serious one will probably cause a malfunction of the synchronous circuit.
As semiconductor process development moves on and the process variation thereof becomes significant, the problem of clock skew is getting worse. Some solution is realized by enhancing the tolerance of the synchronous circuit to clock skew (e.g. adding guard bands to a time sequence and/or setting a clock de-rating factor) or adding a calibration function to the synchronous circuit for clock skew correction. However, if the design requirement of said solution is too loose, the problem of clock skew can't be resolved effectively; on the contrary, if the design requirement is too strict, it will be a waste of the design resource. Therefore, the key to efficiently using the resources is measuring the amount of clock skew accurately. Unfortunately, under the limitation of element precision (e.g. the minimal delay amount of a delay element), the current clock skew detection techniques are merely able to measure the deviation of a clock roughly. Hence, this technical field needs an invention capable of improving the accuracy of clock detection, so as to detect the deviation of a clock correctly for calibration or some utilization.
More prior arts can be found in the following documents: U.S. Pat. No. 6,671,652; and U.S. Pat. No. 7,400,555.